Low Power VLSI
Power Aware or Low Power VLSI designs have become a significant feature to be included in modern day technologies which makes it a topic of research and constant upgrades to do better for future innovations. We have not received one but three PhD thesis service requests for this particular area having different questions and research processes of course. Two of the projects dealt with common and innovative strategies of power dissipation; whereas, the third project dealt with the methods of power estimation in different designs of VLSI chips.
Points We Worked Upon:
- Power Dissipation
- Power Estimation
- Power Reduction
- Power Fixation
- Power Management
Power Management
- VLSI Electronic Designs
- Performance of VLSI Chip
- Low-energy Operational System
- Integrated Circuits
- Future Challenges
Experimental Methods
Experimenting with shrinking technology to increase the complexity of performance by managing power under 100 nm and to see how the optimization of power is not affecting the battery life and package cost.
Innovative Methods
Coming up with hybrid systems by enhancing the already existing designs and systems like CMOS logic style circuits, SERF-FA circuits or modifying XOR gates to optimize the power consumption furthermore.
Technical Methods
This includes effective power management for the System on a Chip (SoC) to provide better and low -power techniques through Integrated Circuits (IC) designs. This includes techniques like clock gating, multi-threshold voltage, DVFS, memory splitting and power gating.
Frequently Asked Questions
Quick Links
Information
CONTACT DETAILS
- 022 4896 4199 (20 Lines)
- 0091 93102 29971
- helpdesk1@mail.phdguidance.org
- Copyright © 2008-2024 PhD Guidance
All Rights Reserved. 
